Digilent 210-179P Bedienungsanleitung PDF herunterladen

™

Revision: July 19, 2011

Note: This document applies to REV C of the board.

1300 NE Henley Court, Suite 3

Pullman, WA 99163

(509) 334 6306 Voice | (509) 334 6300 Fax

Doc: 502-179 page 1 of 6

Overview

The VmodCAM board provides digital imaging

capabilities for any Digilent FPGA system

board with a VHDCI connector. It features two

Aptina MT9D112 2-megapixel CMOS digital

image sensors. The sensors can provide frame

rates from 15 FPS upwards, depending on the

resolution.

Its system-on-a-chip design integrates an

image flow processor and enables selectable

output formats, scaling, and special effects.

The integrated PLL (phase-locked loop) and

microprocessor offer a flexible serial control

interface. The output data is sent on a parallel

bus in processed YCrCb, RGB, or raw Bayer

formats.

Features include:

• two independent Aptina MT9D112 2-

megapixel CMOS digital image sensors

• 1600x1200 maximum resolution at 15

FPS

• 63mm inter-camera spacing (stereo

baseline)

• 10-bit raw color depth

• I

C control bus

• Bayer, RGB, YCrCb output formats

• automatic exposure, gain, and white

balance

• powerful image correction algorithms

• image scaling

• output FIFO

• 68-pin female VHDCI connector

Functional Description

The two MT9D112 cameras can be controlled

independently and can acquire two separate,

simultaneous image feeds. They are controlled

by a two-wire interface.

Each camera has a 2 megapixel color sensor

array in Bayer color filter arrangement. The

sensor readout is 10-bit and supports skipping

or binning rows/columns.

The integrated PLL can generate an internal

clock from the master clock and supports a

wide range of resolutions and frame rates.

The integrated image flow processor applies

correction algorithms to improve image quality.

It can process raw sensor data into RGB or

YCrCb output formats, and crop or scale the

image.

Since some of the processing algorithms

output data in bursts, the parallel output

interface can use a FIFO buffer to provide

constant data rate.

The camera also features a sequencer to

coordinate events triggered by the user.

Operation

The camera systems first need to be properly

configured. This includes not only setting

imaging parameters like resolution or output

format, but PLL configuration and

microprocessor sequencing too. The order in

which these steps are performed is very

important.

1 2 3 4 5 6

Inhaltsverzeichnis

Seite 1 - Operation

VVmmooddCCAAMM™™ RReeffeerreennccee MMaannuuaall Revision: July 19, 2011 Note: This document applies to REV C of the board. 1300 NE Henley Court, S

Seite 2 - Control Interface

Seite 3 - Configuration

Seite 4 - Image Processing

Seite 5

Seite 6 - VHDCI Connector

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